The present invention relates to a method of testing cache memories and, more particularly, to a method of testing cache memories used for an information processing apparatus in which cache memories having different capacities can be mounted.
In general, in an information processing apparatus in which a cache memory can be mounted, in order to guarantee a normal operation, self-diagnosis is performed upon a power-on operation. In this case, a test is performed to check whether the mounted cache memory operates properly.
FIG. 3 shows the cache memory portion of an information processing apparatus in which a cache memory is mounted. FIG. 4 shows processing in this conventional cache memory test method. FIG. 4 shows a portion of the flow chart for self-diagnosis of this information processing apparatus.
As a cache memory, a memory element which operates faster than a main memory is used. This cache memory serves to store copies of frequently accessed data from the main memory and exchange data at a high speed in place of the main memory. A cache memory is generally faster than a main memory but has a small memory capacity.
Referring to FIG. 3, when a CPU 301 generates a request to read data from a main memory 303, the CPU 301 accesses a cache memory 302 first. If the data can be read out ("a cache hit occurs"), the readout data is used. If, however, the data cannot be read out ("a mishit occurs"), the CPU 301 reads out the data from the main memory 303 and uses it. When the data is read out from the main memory 303, it is simultaneously written in the cache memory 302. A cache mishit determining circuit 304 monitors a data write operation with respect to the cache memory 302 to determine the presence/absence of a cache mishit. Referring to FIG. 3, the solid lines indicate the flows of data in the occurrence of a cache hit, and the broken lines indicate the flows of data in the occurrence of a cache mishit.
As data is sequentially written from the main memory 303 into the cache memory 302 upon cache mishits, the cache memory 302 is eventually filled to capacity. After the cache memory 302 becomes full, new data is overwritten on previously written data, thus erasing the old data.
A conventional cache memory test method will be described next with reference to FIG. 4. The same circuit as that shown in FIG. 3 is used.
The conventional cache memory test method is capable of testing two cache memories having different capacities. In this case, two cache memories having capacities of 64 and 128 kilobytes (KB) are mounted in the information processing apparatus to be described in this prior art.
Referring to FIG. 4, in step 401, cache disable processing is performed to inhibit the operation of the cache memory 302. In step 402, test data preparation is performed to cause the main memory 303 to store test data for testing the cache memory 302. As this test data, 128-KB data is formed, which corresponds to the largest capacity of the capacities of the cache memories to be tested.
This test data is set to have regularity in such a manner that each data value coincides with the lower two digits of a corresponding address. For example, a data value "00H" is set for address "10000H". Similarly, "01H" is set for "10001H", . . . , "FFH" for "100FFH", "00H" for "10100H", . . . , "FFH" for "1FFFFH".
In step 403, a test program is copied onto an area other than the cache application area and executed. More specifically, when the CPU 301 accesses the main memory 303, no access to a cache memory is performed in a certain area (an area other than the cache application area) of the main memory. The test program for executing a test is copied in such an area of the main memory 303, i.e., the area other than the cache application area. With this operation, when the test program is read out, the program is not written in a cache memory, thereby preventing data other than test data from being unintentionally written in a cache memory. The program to be executed by the CPU 301 is switched from the currently executed program to the program copied in the area other than the cache application area.
In step 404, cache enable processing is performed to enable the cache memory which has been set in an disabled state. In step 405, all test data is written. That is, the test data is read out from the main memory 303, and all the 128-KB data is written in the cache memory 302, starting from the lower address.
As shown in FIG. 5, when the 128-KB cache memory is used, all the test data is written in the cache memory. If, however, the 64-KB cache memory is used, only 64-KB test data at upper addresses is written in the cache memory. Assume that the 64-KB cache memory is mounted in the information processing apparatus. In this case, when 64-KB test data at lower addresses is read out from the main memory and written in the cache memory, the cache memory is filled to capacity. As the next data is written, the previously written data is sequentially erased upon an overwrite operation. Therefore, when data at addresses corresponding 128 KB is written, only 64-KB test data corresponding to the upper addresses is written in the cache memory.
In step 406, a test data read operation is performed to access the main memory to read out 64-KB test data corresponding to the lower addresses ("10000H" to "1FFFFH" in FIG. 5). The cache mishit determining circuit 304 then checks whether a cache hit or a cache mishit has occurred with respect to each data.
In this case, a data read/write operation based on the program is performed with respect to the main memory 303. When access to the main memory 303 is made, the cache memory 302 is accessed automatically in a hardware manner. The test on the cache memory 302 is performed by using this operation.
In step 407, it is checked whether cache hits have occurred with respect to the all the data. If YES in step 407, it is determined that the capacity of the cache memory is 128 KB. If NO in step 407, it is checked whether cache mishits have occurred with respect to all the data. If YES in step 408, it is determined that the capacity of the cache memory is 64 KB. If NO in step 408, it means that both cache hits and mishits have occurred. In this case, there is a high possibility that a memory failure, a data error, or the like has occurred. Therefore, it is determined that the cache memory has failed. In step 414, error processing is performed.
When a cache mishit occurs with respect to the test data read out from the main memory 303, the data is written in the cache memory not in units of addresses but at a period corresponding to a predetermined cache transfer width. Therefore, when the test data is to be read out, start byte data is read out at the period corresponding to the cache transfer width.
The cache transfer width is the amount of data transferred to the cache memory when a cache mishit occurs. Assume that the cache transfer width is 16 bytes. In this case, when a cache mishit occurs in reading data at address "1000H", data at addresses "1000H" to "1000FH", which corresponds to 16 bytes from the address at which the cache mishit has occurred, is copied in the cache memory. As is apparent, when data at the next address "1001H" is checked, since the data has already been written, a cache hit is determined. Therefore, no check on the data is required.
If YES in step 407, the cache memory mounted in the apparatus is the 128-KB cache memory. In step 409, a test data read operation is performed to read out 128-KB test data again from the main memory, starting from the lower address. The data is written in the cache memory, thereby setting the data in the cache memory again.
Similarly, if YES in step 408, the cache memory mounted in the apparatus is the 64-KB cache memory. In step 410, a test data read operation is performed to read out 64-KB test data again from the main memory, starting from the lower address. The data is written in the cache memory, thereby setting the data in the cache memory again.
In step 411, a test data read operation is performed to read out the 128- or 64-KB data again, which is written in the cache memory in step 409 or 410, from the lower address. In step 412, it is checked whether cache hits have occurred with respect to all the data. If YES in step 412, it is checked in step 413 whether all the data have normal values. If YES in step 413, it is determined that the cache memory is normal.
Note that whether all the data have normal values can be easily determined because the data is set to have regularity in such a manner that each data value coincides with the lower two digits of each address.
If NO is obtained in step 412 or 413 because a cache mishit has occurred or readout data is not normal, error processing is performed in step 414.
In the conventional cache memory test method described above, a test can be performed only when cache memories which can be mounted in an information processing apparatus have two different capacities. For this reason, if cache memories mounted in the information processing apparatus have three or more different capacities upon exchanging or addition of cache memories, a cache memory test cannot be performed.